1. Field of the Invention
This invention relates generally to memory architectures in a computer system and more particularly to architectures for sharing memory among central processing units and peripherals.
2. Description of the Related Art
Computer system performance and costs are affected by the system's memory architecture. Some conventional memory architectures have a fixed memory architecture wherein a certain amount of memory is dedicated to and coupled to a central processing unit (CPU) for exclusive use by the CPU while other memory is dedicated to and coupled to a peripheral such as a computer display. One typical configuration has several megabytes of dynamic random access memory (DRAM) dedicated to the CPU and separate DRAM dedicated for use by a peripheral such as a display device. FIG. 1A illustrates this conventional fixed memory architecture. Under the illustrated architecture, a CPU 101 is coupled to a memory 104 by processor bus 102 and system controller 103. Memory 104 is for example, a conventional DRAM bank dedicated for use by the CPU 101. In the illustrated architecture, system controller 103 is also coupled to a peripheral bus 105 such as a peripheral component interconnect (PCI) bus. Peripheral bus 105 couples CPU 101 to a conventional peripheral controller 106. Under this conventional architecture, peripheral controller 106 is coupled to dedicated peripheral memory 107. Thus, memory 104 is dedicated for use by CPU 101 and peripheral memory 107 is dedicated for use by an associated peripheral controller 106. In this architecture, the peripheral memory 107 (such as memory used as a frame buffer for graphics) dedicated to peripheral controller 106 can be quite large and is often times under-utilized if the peripheral associated with peripheral controller 106 does not require use of the entire memory space provided by memory 107. This under utilization of memory degrades system capability and increases the overall memory cost in a computer system.
Another conventional memory architecture is a unified memory architecture (UMA). Systems having a unified memory architecture generally have decreased system costs and improved memory utilization. These benefits are realized by eliminating peripheral-dedicated memory. One conventional unified memory architecture is shown in FIG. 1B. The illustrated conventional unified memory architecture has a single shared memory bus 108 for coupling CPU 101 and peripheral controllers 106 to memory 104. The illustrated conventional unified memory architecture additionally has a system controller 103 coupled to memory request outputs of CPU 101 and peripheral controllers 106. System controller 103 arbitrates access of memory 104 by peripheral controllers 106 and CPU 101 to eliminate memory collisions. This memory access arbitration, however, can take several clock cycles and thus degrades system performance.
Thus, there is a need for a memory architecture that improves memory utilization, decreases overall system memory requirements and costs and does not degrade system performance.